0 – July. 1. Qualification Package. AT89C51ED2. FLASH 8-bit C51 Microcontroller. 64 Kbytes FLASH, 2 Kbytes EEPROM. AT89C51RD2 / AT89C51ED2. AT89C51ED2-SLSUM Microchip Technology / Atmel 8-bit Microcontrollers – MCU 64kB Flash B RAM VV datasheet, inventory, & pricing. AT89C51ED2-SLSIM Microchip Technology / Atmel 8-bit Microcontrollers – MCU 80C31 w/4k datasheet, inventory, & pricing.
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Set to enable KBF. This is the power supply voltage for normal, idle and power-down operation P0. Page datasheet Figure It is driven by the Master for eight clock cycles which allows to exchange one Byte on the serial lines. Symbol Description Symbol Table The programming voltage is internally generated from the standard VCC pin. All other vectors addresses are the same as standard C52 devices.
Timer 2 operation is similar to Timer 0 and Timer 1.
Page 62 Table Page 58 Table MODF is set to warn that there may be a multimaster conflict for system control. This is achieved by applying an internal reset to them. This output type can be used as both an input and output without the need to reconfigure the port.
Set to configure the SPI as a Master. Do not set this bit. Setting TR2 allows TL2 to increment by the selected input. Save and disable interrupts.
MICROCHIP TECHNOLOGY AT89C51ED2-SLRUM : Datasheet
Page 18 Figure Clear to select 6 clock periods per peripheral clock cycle. Oscillator To optimize the power consumption and execution time needed for a specific task, an internal prescaler feature has been implemented between the oscillator and the CPU and peripherals.
This signal must stay low for any message for a Slave. Set to select 12 clock periods per peripheral clock cycle. A cold start reset is the one induced by VCC switch-on. Page 42 Table Page 38 Table Set to enable all interrupts. By default, Standard mode is active. Flow Description Overview An initialization step must be performed after each Reset.
Set by user for general purpose usage. It is obvious that only one Master SS high level can drive the network.
When the pin is pulled low, it is driven strongly and able ay89c51ed2 sink a fairly large current. Page 78 Table Set by hardware when an invalid stop bit is detected.
Set by hardware when VCC rises from 0 to its nominal voltage. This can be useful if external peripherals are mapped at addresses already used by the internal XRAM. Page 10 NIC P2.