January JEDEC. STANDARD. DDR2 SDRAM SPECIFICATION be addressed to JEDEC Solid State Technology Association, Wilson Boulevard. DDR2 SDRAM is a double data rate synchronous dynamic random-access memory interface. It superseded the original DDR SDRAM specification, and is superseded by .. JEDEC standard: DDR2 SDRAM Specification: JESDF, November ** ยท JEDEC. The JEDEC memory standards are the specifications for semiconductor memory circuits and Memory modules of the DDR2-SDRAM type are available for laptop, desktop, and server computers in a wide selection of capacities and access.

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DDR2’s bus frequency is boosted by electrical interface improvements, on-die terminationprefetch buffers and off-chip drivers.

JEDEC memory standards

The documentation of modern memory modules, such as the standards ddrr2 the memory ICs [4] and a reference design of the module [5] requires over one hundred pages. An alternative system is found specificcation Amendment 2 to IEC However, further confusion has been added to the mix with jeddc appearance of budget and mid-range graphics cards which claim to use “GDDR2”.

In other projects Wikimedia Commons. Please update this article to reflect recent events or newly available information. Retrieved from ” https: During an access, four bits were read or written jeedc or from a four-bit-deep prefetch queue.

Archived from the original on The specification contains definitions of the commonly used prefixes kilomegaand giga usually combined with the units byte and bit to designate multiples of the units. Power savings are achieved primarily due to an improved manufacturing process through die shrinkage, resulting in a drop in operating voltage 1. This queue received or transmitted its data over the data bus in two data bus clock cycles each clock cycle transferred two bits of data.


The document notes that these prefixes are used in their decimal sense for serial communication data rates measured in bits. Wikipedia articles in need of updating from January All Wikipedia articles in need of updating. From Wikipedia, the free encyclopedia. This page was last edited on 2 Augustat The two factors combine to produce a total of four data transfers per internal clock cycle. By using this site, you agree to the Terms of Use and Privacy Policy.

These chips cannot achieve the clock rates of GDDR3 but are inexpensive and fast enough to be used as memory on mid-range cards. This page was last edited on 11 Januaryat At least one manufacturer has reported this reflects successful testing at a higher-than-standard data rate [4] whilst others simply round up for the name. These cards actually use standard DDR2 chips designed for use as main system memory although operating with higher latencies to achieve higher clockrates.

JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. Alternatively, DDR2 memory operating at twice the external data bus clock rate as DDR may provide twice the bandwidth with the same latency.


The definitions of kilo, giga, and mega based on powers of two are included only to reflect common usage. The purpose of the standard is to promote the uniform use of symbols, abbreviations, terms, and definitions throughout the semiconductor industry.


This committee consists of members from manufacturers of microprocessors, memory ICs, memory modules, and other components, as well as component integrators, nedec as video card and personal computer makers. The standards specify the physical and electrical characteristics of the modules, and include the data for computer simulations of the memory module operating in a system.

DDR2 was introduced in the second quarter of at two initial clock rates: These chips are mostly standard DDR chips that have been tested and rated to be capable of operation at higher clock rates by the manufacturer. Retrieved from ” https: Dynamic random-access memory DRAM.


Views Read Edit View history. DDR2 started specificatiin become competitive against the older DDR standard by the end ofas modules with lower latencies became available.

From Wikipedia, the free encyclopedia. The specification notes that these prefixes are included in the document only to reflect common usage. DIMMs are identified by their peak transfer capacity often called bandwidth. Both performed worse than the original DDR specification due to higher latency, which made total access times longer.